The present invention relates to a driving device and a driving method for an ink jet printing head which conducts printing by discharging ink drops from nozzles by changing the volumes of pressure generation chambers filled with ink according to driving signals which are supplied to piezoelectric actuators etc., and in particular, to a driving device and a driving method for an ink jet printing head that improves the expressiveness of gradation and halftones in print images by changing the size of ink dots which are formed on paper etc. by varying the ink drip size based on print data indicating halftones.
Printing of halftone images on paper etc. has been conducted generally by binary image printing by use of image processing techniques such as the xe2x80x9cdot area modulation methodxe2x80x9d and the xe2x80x9cscreened half tone (screening)xe2x80x9d. However, image printing of photographic-quality is being required in recent years and thereby printing by use of ink drop size modulation techniques is being required of ink jet printing heads.
A driving device for an ink jet printing head for meeting the request has been disclosed in Japanese Patent Application Laid-Open No.HEI9-11457 (hereafter, referred to as xe2x80x9cdocument No.1xe2x80x9d), in which two or more driving signals for the discharge of ink drops of different sizes are prepared, and the driving signals are selectively used based on image data.
FIG. 1 is a block diagram showing an example of a conventional ink jet printing head driving device for implementing the ink drop size modulation technique disclosed in the document No.1. The ink jet printing head driving device shown in FIG. 1 includes a common waveform generation circuit 101, an image memory 131, a data transmission circuit 132, a data reception circuit 143, a decoder 142, a level conversion circuit 141 and multiplexers 121-1xcx9c121-n. The multiplexers 121-1xcx9c121-n are provided corresponding to piezoelectric actuators 123-1xcx9c123-n of the ink jet printing head. The common waveform generation circuit 101 includes a waveform generation circuit 111 and two or more voltage/current amplification circuits 112. In the example of FIG. 1, the common waveform generation circuit 101 includes three voltage/current amplification circuits 112Axcx9c112C. Each multiplexer 121-k (1xe2x89xa6kxe2x89xa6n) which is composed of transfer gates selects (zero or) one of the voltage/current amplification circuits 112Axcx9c112C according to image data (print data) indicating a halftone, and a driving signal (VD1, VD2 or VD3) that is supplied from the selected voltage/current amplification circuit (112A, 112B or 112C) is transmitted by the multiplexer 121-k and is applied to a corresponding piezoelectric actuator 123-k (1xe2x89xa6kxe2x89xa6n), thereby printing of halftone images is conducted.
However, in the technique of the document No. 1, each voltage/current amplification circuit 112 (112A, 112B, 112C) of the common waveform generation circuit 101 is designed to drive a plurality of piezoelectric actuators 123-1xcx9c123-n through the multiplexers 121-1xcx9c121-n, thereby waveform distortion of the driving signal occurs considerably between the voltage/current amplification circuit 112 (112A, 112B, 112C) and the piezoelectric actuators 123 (123-1xcx9c123-n) due to wire resistance and inductance. Further, the distortion of the driving signal varies depending on the number of piezoelectric actuators 123 that are driven simultaneously.
The above problems come up since a driving signal of a very high slew rate (dV/dt) has to be supplied to the piezoelectric actuator 123 which is a relatively large capacitive load. The very high slew rate of the driving signal is necessary for the formation and discharge of minute ink drops of approximately 2 pl (picoliter) which is required for high quality printing by means of the ink drop size modulation.
If we assume that the capacitance of a piezoelectric actuator 123 is C0 (pF) and the number of driven piezoelectric actuators 123 is n, the load on the voltage/current amplification circuit 112 becomes nxc3x97C0. In a typical case where the number n is 300 and the capacitance C0 is 3000 (pF), the load on the voltage/current amplification circuit 112 becomes nxc3x97C0=0.9 (xcexcF). In order to realize the discharge of the picoliter ink drops, application of high-frequency voltage between the voltage/current amplification circuit 112 and the piezoelectric actuators 123 is required as a matter of course, therefore, considerable signal distortion is caused due to the wire resistance and inductance between the voltage/current amplification circuit 112 and the piezoelectric actuators 123. Further, the signal distortion varies depending on the number of simultaneously driven piezoelectric actuators 123 as mentioned above. Therefore, the sizes of discharged ink drops and printed ink dots are necessitated to vary and fluctuate.
For the printing of characters or letters, the ink jet printing head is required to discharge ink drops of large sizes. In such cases, a driving signal (waveform) having a large voltage variation has to be applied to each piezoelectric actuator 123. When the voltage of the driving signal changes from V0 (V) to V1 (V), heat emission P (W) of the voltage/current amplification circuit 112 is calculated as: (xc2xd)xc3x97nxc3x97C0xc3x97(V12xe2x88x92V02). Therefore, the heat emission of the voltage/current amplification circuit 112 increases as the voltage variation (V1xe2x88x92V0) of the driving waveform gets larger.
The heat emission also changes proportionally to the number of simultaneously driven piezoelectric actuators 123, therefore, the heat emission of the voltage/current amplification circuit 112 further increases when the number of nozzles (that is, the number of piezoelectric actuators 123) of the ink jet printing head is set larger in order to realize high speed printing.
When the multiplexers 121-1xcx9c121-n are implemented as an IC, each multiplexer 121 (121-1xcx9c121-n) is generally implemented as transfer gates each of which includes an N-MOSFET and a P-MOSFET. Therefore, when each multiplexer 121 includes three transfer gates as the example of FIG. 1, three N-MOSFETs and three P-MOSFETs become necessary in a multiplexer 121. Current for driving the piezoelectric actuators 123 has to be passed through each MOSFET, therefore, channel resistance of each MOSFET has to be set as small as possible in order to reduce heat emission of the multiplexer 121. However, in order to set the channel resistance small, chip size of the IC is necessitated to be large, and thus high integration of the IC becomes difficult.
A driving device for an ink jet printing head designed for eliminating the heat emission problem of the common waveform generation circuit and the waveform distortion of the driving signal supplied to the piezoelectric actuators has been disclosed in Japanese Patent Application Laid-Open No.HEI9-174883 (hereafter, referred to as xe2x80x9cdocument No.2xe2x80x9d).
FIG. 2 is a block diagram showing an example of a conventional ink jet printing head driving device which implements the techniques disclosed in the document No.2. In the ink jet printing head driving device of FIG. 2, each multiplexer (221-1xcx9c221-n) is provided with a corresponding voltage amplification circuit (212-1xcx9c212-n) before itself and a corresponding current amplification circuit (222-1xcx9c222-n) after itself.
By such composition of the ink jet printing head driving device for driving piezoelectric actuators 223-1xcx9c223-n, the heat emission problem of the common waveform generation circuit 201 and the waveform distortion of the driving signals supplied to the piezoelectric actuators 223-1xcx9c223-n are avoided.
However, considering the voltage amplification factor required of the voltage amplification circuit (212-1xcx9c212-n) amplifying the driving waveforms, it is preferable that the voltage amplification circuit (212-1xcx9c212-n) should be composed of a negative feedback amplification circuit. Voltage that has to be applied to the piezoelectric actuators 223-1xcx9c223-n is on the order of 10V, therefore, each voltage amplification circuit (212-1xcx9c212-n) has to be composed of parts withstanding such high voltage. If a plurality of such high-voltage-resistant voltage amplification circuits 212-1xcx9c212-n are integrated onto an IC, circuit scale (chip size) of the IC is necessitated to be too large and the degree of integration of the IC is necessitated to be very low.
Further, when the circuit shown in FIG. 2 is integrated onto an IC, circuits having high voltage amplification factors have to be packed close to each other, thereby current crosstalk between the voltage amplification circuits 212-1xcx9c212-n is caused.
Further, such a circuit having a high voltage amplification factor tends to become unstable by heat. If the heat-emitting current amplification circuits 222-1xcx9c222-n are closely packed in the IC, the operation of the voltage amplification circuits 212-1xcx9c212-n tends to be unstable due to the heat emission of the closely packed current amplification circuits 222-1xcx9c222-n. 
FIG. 3A is a circuit diagram showing a first example of the composition of the current amplification circuit 222 (222-1xcx9c222-n) which has been disclosed in the document No.2. The current amplification circuit 222 shown in FIG. 3A has emitter follower structure by use of an NPN transistor Q202 and a PNP transistor Q203. However, such circuit composition involves the following problems or drawbacks.
First, the current amplification circuit 222 of FIG. 3A is composed of transistors, and thus the response of the current amplification circuit 222 to the driving signal having the relatively high slew rate becomes slow, therefore, there is a possibility of a cross current passing between the transistors Q202 and Q203. For the prevention of the cross current, a PNP transistor Q201 and an NPN transistor Q204 have to be added as shown in FIG. 3A.
Second, in the circuit composition of FIG. 3A, no bias voltage is applied between the gates of the NPN transistor Q202 and the PNP transistor Q203, therefore, crossover distortion occurs due to voltage between the base and emitter of each transistor.
FIG. 3B is a circuit diagram showing a second example of the composition of the current amplification circuit 222 (222-1xcx9c222-n) which has been disclosed in the document No.2. The current amplification circuit 222 of FIG. 3B is composed of a P-MOSFET Q211, an N-MOSFET Q212 and operational amplifiers OP201 and OP202. The operational amplifiers OP201 and OP202 are provided as gate inputs to the P-MOSFET Q211 and the N-MOSFET Q212. However, it is evident that the voltage level of the driving signal inputted to the current amplification circuit 222 exceeds at least 30 V. Therefore, it is substantially impossible to implement an IC including the current amplification circuits 222 of FIG. 3B employing operational amplifiers withstanding such high voltage.
It is therefore the primary object of the present invention to provide a driving device and a driving method for an ink jet printing head, by which the waveform distortion of the driving signals supplied to the piezoelectric actuators of the ink jet printing head can be reduced even if the piezoelectric actuator is of large load capacitance, the heat emission of the voltage amplification circuits of the common waveform generation circuit can be reduced, and high circuit integration of the driving circuit can be realized.
In accordance with a first aspect of the present invention, there is provided a driving device for an ink jet printing head which is capable of discharging ink drops from its N (N=1, 2, 3, . . . ) nozzles by changing the volumes of pressure generation chambers filled with ink. The driving device comprises a waveform generation means, a voltage amplification means, N selective transmission means, and N current amplification means. The waveform generation means generates a waveform for a driving signal. The voltage amplification means amplifies the voltage level of the waveform generated by the waveform generation means and thereby outputs the driving signal. The N selective transmission means are provided corresponding to the N nozzles. Each of the N selective transmission means selectively transmits the driving signal supplied from the voltage amplification means. The N current amplification means are provided corresponding to the N selective transmission means. Each of the N current amplification means amplifies the current level of the driving signal that has passed the corresponding selective transmission means and thereby supplies the current-amplified driving signal to a corresponding piezoelectric actuator so that the volume of a corresponding pressure generation chamber will be changed and the ink drop discharge will be conducted from a corresponding nozzle according to the current-amplified driving signal.
In accordance with a second aspect of the present invention, in the first aspect, the waveform generation means generates M (M=1, 2, 3, . . . ) types of waveforms, and the driving device includes M voltage amplification means corresponding to the M waveforms. Each of the M voltage amplification means amplifies the voltage level of corresponding one of the M waveforms and thereby outputs a driving signal. Each of the N selective transmission means transmits zero or one of the M driving signals outputted by the M voltage amplification means based on one or more selection control signals supplied thereto.
In accordance with a third aspect of the present invention, in the first aspect, the voltage amplification means is designed to have low output impedance.
In accordance with a fourth aspect of the present invention, in the third aspect, the voltage amplification means includes an impedance conversion circuit for reducing the output impedance of the voltage amplification means as its output stage for outputting the driving signal.
In accordance with a fifth aspect of the present invention, in the fourth aspect, the voltage amplification means further includes a feedback circuit and a differential amplification circuit. The feedback circuit returns part of the driving signal outputted by the voltage amplification means as a feedback voltage. The differential amplification circuit compares the waveform supplied from the waveform generation means with the feedback voltage supplied from the feedback circuit and amplifies the waveform according to the result of the comparison.
In accordance with a sixth aspect of the present invention, in the fifth aspect, the feedback circuit supplies the feedback voltage to the differential amplification circuit compensating for phase delay of the driving signal with respect to the waveform supplied to the differential amplification circuit.
In accordance with a seventh aspect of the present invention, in the fifth aspect, the voltage amplification means further includes a Miller integration circuit for further amplifying the waveform amplified by the differential amplification circuit.
In accordance with an eighth aspect of the present invention, in the seventh aspect, the voltage amplification means further includes a first constant-current circuit for supplying a constant current to the Miller integration circuit.
In accordance with a ninth aspect of the present invention, in the eighth aspect, the voltage amplification means further includes a first bias circuit for converting the waveform which has been further amplified by the Miller integration circuit to a bias voltage.
In accordance with a tenth aspect of the present invention, in the eighth aspect, the voltage amplification means further includes a buffer which is provided between the first constant-current circuit and the impedance conversion circuit so that the load on the Miller integration circuit will not be composed of a parallel connection of the load impedance of the first constant-current circuit and the capacitance of the impedance conversion circuit.
In accordance with an eleventh aspect of the present invention, in the fourth aspect, the impedance conversion circuit is designed to have single-ended push-pull (SEPP) structure.
In accordance with a twelfth aspect of the present invention, in the fourth aspect, the impedance conversion circuit includes: a first resistor and a second resistor which are connected in series; a first N-MOSFET whose drain is supplied with power supply voltage and whose source is connected to an end of the first resistor opposite to the second resistor; and a first P-MOSFET whose source is connected to and end of the second resistor opposite to the first resistor and whose drain is grounded. The output of the impedance conversion circuit is taken from wiring between the first resistor and the second resistor.
In accordance with a thirteenth aspect of the present invention, in the fifth aspect, the feedback circuit includes: a phase lead circuit which is composed of a third resistor and a first capacitor connected in parallel; and a fourth resistor which is connected to the output side of the phase lead circuit to be grounded.
In accordance with a fourteenth aspect of the present invention, in the fifth aspect, the differential amplification circuit includes: a first PNP transistor and a second PNP transistor having equivalent characteristics; a fifth resistor whose one end is connected to the emitters of the first PNP transistor and the second PNP transistor and whose other end is supplied with power supply voltage; and a sixth resistor whose one end is connected to the collector of the first PNP transistor and whose other end is connected to the collector of the second PNP transistor which is grounded. The waveform supplied from the waveform generation means is applied to the base of the first PNP transistor. The feedback voltage supplied from the feedback circuit is applied to the base of the second PNP transistor.
In accordance with a fifteenth aspect of the present invention, in the seventh aspect, the Miller integration circuit is implemented as a grounded-emitter circuit.
In accordance with a sixteenth aspect of the present invention, in the ninth aspect, the Miller integration circuit includes: a first NPN transistor whose base is supplied with the waveform amplified by the differential amplification circuit and whose collector is connected to the first bias circuit and whose emitter is grounded; and a second capacitor which is connected between the base and collector of the first NPN transistor.
In accordance with a seventeenth aspect of the present invention, in the eighth aspect, the first constant-current circuit is designed to have current mirror structure.
In accordance with an eighteenth aspect of the present invention, in the ninth aspect, the first constant-current circuit includes: a third PNP transistor and a fourth PNP transistor having equivalent characteristics and whose bases are connected together; a seventh resistor whose one end is connected to the emitter of the third PNP transistor and whose other end is supplied with power supply voltage; an eighth resistor whose one end is connected to the emitter of the fourth PNP transistor and whose other end is supplied with the power supply voltage; and a ninth resistor whose one end is connected to the collector of the third PNP transistor and whose other end is grounded. The collector of the third PNP transistor is connected to the bases of the third PNP transistor and the fourth PNP transistor. The collector of the fourth PNP transistor is connected to the Miller integration circuit via the first bias circuit.
In accordance with a nineteenth aspect of the present invention, in the ninth aspect, the first bias circuit includes: a second NPN transistor; a tenth resistor whose one end is connected to the first constant-current circuit and the collector of the second NPN transistor and whose other end is connected to the base of the second NPN transistor; and an eleventh resistor whose one end is connected to wiring between the tenth resistor and the base of the second NPN transistor and whose other end is connected to the emitter of the second NPN transistor and the Miller integration circuit.
In accordance with a twentieth aspect of the present invention, in the tenth aspect, the buffer is designed to have emitter follower structure.
In accordance with a twenty-first aspect of the present invention, in the nineteenth aspect, the buffer includes: a twelfth resistor and a thirteenth resistor which are connected in series; a third NPN transistor whose collector is supplied with power supply voltage and whose base is connected to the collector of the second NPN transistor of the first bias circuit and whose emitter is connected to an end of the twelfth resistor opposite to the thirteenth resistor; and a fifth PNP transistor whose emitter is connected to an end of the thirteenth resistor opposite to the twelfth resistor and whose base is connected to the emitter of the second NPN transistor of the first bias circuit and whose collector is grounded.
In accordance with a twenty-second aspect of the present invention, in the twenty-first aspect, the impedance conversion circuit includes: a first resistor and a second resistor which are connected in series; a first N-MOSFET whose drain is supplied with power supply voltage and whose gate is connected to the emitter of the third NPN transistor of the buffer and whose source is connected to an end of the first resistor opposite to the second resistor; and a first P-MOSFET whose source is connected to and end of the second resistor opposite to the first resistor and whose gate is connected to the emitter of the fifth PNP transistor of the buffer and whose drain is grounded. The output of the impedance conversion circuit is taken from wiring between the first resistor and the second resistor.
In accordance with a twenty-third aspect of the present invention, in the twenty-second aspect, the wiring between the first resistor and the second resistor of the impedance conversion circuit from which the output of the impedance conversion circuit is taken is connected to wiring between the twelfth resistor and the thirteenth resistor of the buffer.
In accordance with a twenty-fourth aspect of the present invention, in the thirteenth aspect, the output of the impedance conversion circuit is supplied to the phase lead circuit of the feedback circuit.
In accordance with a twenty-fifth aspect of the present invention, in the first aspect, the current amplification means includes: a second bias circuit for converting the driving signal that passed the corresponding selective transmission means to a bias voltage; and a first source follower having single-ended push-pull (SEPP) structure.
In accordance with a twenty-sixth aspect of the present invention, in the twenty-fifth aspect, the second bias circuit of the current amplification means includes: a fourteenth resistor and a fifteenth resistor which are connected in series and which receive the driving signal from the corresponding selective transmission means at wiring therebetween; a second constant-current circuit whose input terminal is supplied with power supply voltage and whose output terminal is connected to an end of the fourteenth resistor opposite to the fifteenth resistor; and a third constant-current circuit whose input terminal is connected to an end of the fifteenth resistor opposite to the fourteenth resistor and whose output terminal is grounded.
In accordance with a twenty-seventh aspect of the present invention, in the twenty-sixth aspect, the first source follower of the current amplification means includes: a second N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the output terminal of the second constant-current circuit; and a second P-MOSFET whose source is connected to the source of the second N-MOSFET and whose gate is connected to the input terminal of the third constant-current circuit and whose drain is grounded. The output of the current amplification means is taken from wiring between the sources of the second N-MOSFET and the second P-MOSFET.
In accordance with a twenty-eighth aspect of the present invention, in the twenty-fifth aspect, the first source follower of the current amplification means includes two MOSFETs, and the second bias circuit of the current amplification means includes two MOSFETs corresponding to the two MOSFETs of the first source follower. Each MOSFET of the first source follower has polarity that is opposite to that of the corresponding MOSFET of the second bias circuit.
In accordance with a twenty-ninth aspect of the present invention, in the twenty-fifth aspect, the second bias circuit of the current amplification means includes: a third P-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means and whose drain is grounded; a third N-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means and whose drain is supplied with power supply voltage; a sixteenth resistor whose one end is supplied with the power supply voltage and whose other end is connected to the source of the third P-MOSFET; and a seventeenth resistor whose one end is connected to the source of the third N-MOSFET and whose other end is grounded.
In accordance with a thirtieth aspect of the present invention, in the twenty-ninth aspect, the first source follower of the current amplification means includes: a fourth N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the source of the third P-MOSFET; and a fourth P-MOSFET whose source is connected to the source of the fourth N-MOSFET and whose gate is connected to the source of the third N-MOSFET and whose drain is grounded. The output of the current amplification means is taken from wiring between the sources of the fourth N-MOSFET and the fourth P-MOSFET.
In accordance with a thirty-first aspect of the present invention, in the first aspect, the current amplification means includes: a fourth constant-current circuit; and a second source follower having single-ended push-pull (SEPP) structure.
In accordance with a thirty-second aspect of the present invention, in the thirty-first aspect, the fourth constant-current circuit is designed to have current mirror structure.
In accordance with a thirty-third aspect of the present invention, in the thirty-second aspect, the current amplification means includes: a fifth P-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means; an eighteenth resistor whose one end is supplied with power supply voltage and whose other end is connected to the source of the fifth P-MOSFET; a fifth N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the source of the fifth P-MOSFET; a sixth N-MOSFET whose drain is connected to the drain of the fifth P-MOSFET; a seventh N-MOSFET whose drain is connected to the source of the fifth N-MOSFET and whose gate is connected to the gate of the sixth N-MOSFET and the drain of the fifth P-MOSFET; a nineteenth resistor whose one end is connected to the source of the sixth N-MOSFET and whose other end is grounded; and a twentieth resistor whose one end is connected to the source of the seventh N-MOSFET and whose other end is grounded. The output of the current amplification means is taken from wiring between the source of the fifth N-MOSFET and the drain of the seventh N-MOSFET.
In accordance with a thirty-fourth aspect of the present invention, in the second aspect, the waveform generation means refers to variables which have preliminarily been stored in the driving device for specifying the M types of waveforms and thereby generates the M waveforms according to the variables.
In accordance with a thirty-fifth aspect of the present invention, in the second aspect, the selective transmission means includes M transfer gates each of which is composed of two MOSFETs.
In accordance with a thirty-sixth aspect of the present invention, there is provided a driving method for an ink jet printing head which is capable of discharging ink drops from its N (N=1, 2, 3, . . . ) nozzles by changing the volumes of pressure generation chambers filled with ink. The driving method comprises a waveform generation step, a voltage amplification step, a selective transmission step and a current amplification step. In the waveform generation step, a waveform for a driving signal is generated. In the voltage amplification step, the voltage level of the waveform generated in the waveform generation step is amplified and thereby the driving signal is obtained. In the selective transmission step, the driving signal obtained in the voltage amplification step is selectively transmitted by N selective transmission means corresponding to the N nozzles individually and simultaneously. In the current amplification step, the current level of each driving signal that passed each of the N selective transmission means in the selective transmission step is amplified by each of corresponding N current amplification means individually to be supplied to a corresponding piezoelectric actuator so that the volume of a corresponding pressure generation chamber will be changed and the ink drop discharge will be conducted from a corresponding nozzle according to the current-amplified driving signal.
In accordance with a thirty-seventh aspect of the present invention, in the thirty-sixth aspect, M (M=1, 2, 3, . . . ) types of waveforms are generated in the waveform generation step. The voltage level of each of the M waveforms is amplified individually and thereby M driving signals are obtained in the voltage amplification step. Zero or one of the M driving signals obtained in the voltage amplification step is selected and transmitted by each of the N selective transmission means individually and simultaneously based on one or more selection control signals supplied to each selective transmission means in the selective transmission step.
In accordance with a thirty-eighth aspect of the present invention, in the thirty-sixth aspect, a voltage amplification means having low output impedance is used for the voltage amplification step.
In accordance with a thirty-ninth aspect of the present invention, in the thirty-eighth aspect, the voltage amplification step is conducted employing an impedance conversion circuit for reducing output impedance as the output stage of the voltage amplification means.
In accordance with a fortieth aspect of the present invention, in the thirty-ninth aspect, the voltage amplification step is conducted further employing a feedback circuit and a differential amplification circuit. The feedback circuit returns part of the driving signal obtained in the voltage amplification step as a feedback voltage. The differential amplification circuit compares the waveform generated in the waveform generation step with the feedback voltage supplied from the feedback circuit and amplifies the waveform according to the result of the comparison.
In accordance with a forty-first aspect of the present invention, in the fortieth aspect, the feedback circuit supplies the feedback voltage to the differential amplification circuit compensating for phase delay of the driving signal with respect to the waveform supplied to the differential amplification circuit.
In accordance with a forty-second aspect of the present invention, in the fortieth aspect, the voltage amplification step is conducted further employing a Miller integration circuit for further amplifying the waveform amplified by the differential amplification circuit.
In accordance with a forty-third aspect of the present invention, in the forty-second aspect, the voltage amplification step is conducted further employing a first constant-current circuit for supplying a constant current to the Miller integration circuit.
In accordance with a forty-fourth aspect of the present invention, in the forty-third aspect, the voltage amplification step is conducted further employing a first bias circuit for converting the waveform which has been further amplified by the Miller integration circuit to a bias voltage.
In accordance with a forty-fifth aspect of the present invention, in the forty-third aspect, the voltage amplification step is conducted further employing a buffer which is provided between the first constant-current circuit and the impedance conversion circuit so that the load on the Miller integration circuit will not be composed of a parallel connection of the load impedance of the first constant-current circuit and the capacitance of the impedance conversion circuit.
In accordance with a forty-sixth aspect of the present invention, in the thirty-ninth aspect, the impedance conversion circuit is designed to have single-ended push-pull (SEPP) structure.
In accordance with a forty-seventh aspect of the present invention, in the thirty-ninth aspect, the impedance conversion circuit includes: a first resistor and a second resistor which are connected in series; a first N-MOSFET whose drain is supplied with power supply voltage and whose source is connected to an end of the first resistor opposite to the second resistor; and a first P-MOSFET whose source is connected to and end of the second resistor opposite to the first resistor and whose drain is grounded. The output of the impedance conversion circuit is taken from wiring between the first resistor and the second resistor.
In accordance with a forty-eighth aspect of the present invention, in the fortieth aspect, the feedback circuit includes: a phase lead circuit which is composed of a third resistor and a first capacitor connected in parallel; and a fourth resistor which is connected to the output side of the phase lead circuit to be grounded.
In accordance with a forty-ninth aspect of the present invention, in the fortieth aspect, the differential amplification circuit includes: a first PNP transistor and a second PNP transistor having equivalent characteristics; a fifth resistor whose one end is connected to the emitters of the first PNP transistor and the second PNP transistor and whose other end is supplied with power supply voltage; and a sixth resistor whose one end is connected to the collector of the first PNP transistor and whose other end is connected to the collector of the second PNP transistor which is grounded. The waveform generated in the waveform generation step is applied to the base of the first PNP transistor, The feedback voltage supplied from the feedback circuit is applied to the base of the second PNP transistor.
In accordance with a fiftieth aspect of the present invention, in the forty-second aspect, the Miller integration circuit is implemented as a grounded-emitter circuit.
In accordance with a fifty-first aspect of the present invention, in the forty-fourth aspect, the Miller integration circuit includes: a first NPN transistor whose base is supplied with the waveform amplified by the differential amplification circuit and whose collector is connected to the first bias circuit and whose emitter is grounded; and a second capacitor which is connected between the base and collector of the first NPN transistor.
In accordance with a fifty-second aspect of the present invention, in the forty-third aspect, the first constant-current circuit is designed to have current mirror structure.
In accordance with a fifty-third aspect of the present invention, in the forty-fourth aspect, the first constant-current circuit includes: a third PNP transistor and a fourth PNP transistor having equivalent characteristics and whose bases are connected together; a seventh resistor whose one end is connected to the emitter of the third PNP transistor and whose other end is supplied with power supply voltage; an eighth resistor whose one end is connected to the emitter of the fourth PNP transistor and whose other end is supplied with the power supply voltage; and a ninth resistor whose one end is connected to the collector of the third PNP transistor and whose other end is grounded. The collector of the third PNP transistor is connected to the bases of the third PNP transistor and the fourth PNP transistor. The collector of the fourth PNP transistor is connected to the Miller integration circuit via the first bias circuit.
In accordance with a fifty-fourth aspect of the present invention, in the forty-fourth aspect, the first bias circuit includes: a second NPN transistor; a tenth resistor whose one end is connected to the first constant-current circuit and the collector of the second NPN transistor and whose other end is connected to the base of the second NPN transistor; and an eleventh resistor whose one end is connected to wiring between the tenth resistor and the base of the second NPN transistor and whose other end is connected to the emitter of the second NPN transistor and the Miller integration circuit.
In accordance with a fifty-fifth aspect of the present invention, in the forty-fifth aspect, the buffer is designed to have emitter follower structure.
In accordance with a fifty-sixth aspect of the present invention, in the fifty-fourth aspect, the buffer includes: a twelfth resistor and a thirteenth resistor which are connected in series; a third NPN transistor whose collector is supplied with power supply voltage and whose base is connected to the collector of the second NPN transistor of the first bias circuit and whose emitter is connected to an end of the twelfth resistor opposite to the thirteenth resistor; and a fifth PNP transistor whose emitter is connected to an end of the thirteenth resistor opposite to the twelfth resistor and whose base is connected to the emitter of the second NPN transistor of the first bias circuit and whose collector is grounded.
In accordance with a fifty-seventh aspect of the present invention, in the fifty-sixth aspect, the impedance conversion circuit includes: a first resistor and a second resistor which are connected in series; a first N-MOSFET whose drain is supplied with power supply voltage and whose gate is connected to the emitter of the third NPN transistor of the buffer and whose source is connected to an end of the first resistor opposite to the second resistor; and a first P-MOSFET whose source is connected to and end of the second resistor opposite to the first resistor and whose gate is connected to the emitter of the fifth PNP transistor of the buffer and whose drain is grounded. The output of the impedance conversion circuit is taken from wiring between the first resistor and the second resistor.
In accordance with a fifty-eighth aspect of the present invention, in the fifty-seventh aspect, the wiring between the first resistor and the second resistor of the impedance conversion circuit from which the output of the impedance conversion circuit is taken is connected to wiring between the twelfth resistor and the thirteenth resistor of the buffer.
In accordance with a fifty-ninth aspect of the present invention, in the forty-eighth aspect, the output of the impedance conversion circuit is supplied to the phase lead circuit of the feedback circuit.
In accordance with a sixtieth aspect of the present invention, in the thirty-sixth aspect, the current amplification means which is used for the current amplification step includes: a second bias circuit for converting the driving signal that passed the corresponding selective transmission means in the selective transmission step to a bias voltage; and a first source follower having single-ended push-pull (SEPP) structure.
In accordance with a sixty-first aspect of the present invention, in the sixtieth aspect, the second bias circuit of the current amplification means includes: a fourteenth resistor and a fifteenth resistor which are connected in series and which receive the driving signal from the corresponding selective transmission means at wiring therebetween; a second constant-current circuit whose input terminal is supplied with power supply voltage and whose output terminal is connected to an end of the fourteenth resistor opposite to the fifteenth resistor; and a third constant-current circuit whose input terminal is connected to an end of the fifteenth resistor opposite to the fourteenth resistor and whose output terminal is grounded.
In accordance with a sixty-second aspect of the present invention, in the sixty-first aspect, the first source follower of the current amplification means includes: a second N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the output terminal of the second constant-current circuit; and a second P-MOSFET whose source is connected to the source of the second N-MOSFET and whose gate is connected to the input terminal of the third constant-current circuit and whose drain is grounded. The output of the current amplification means is taken from wiring between the sources of the second N-MOSFET and the second P-MOSFET.
In accordance with a sixty-third aspect of the present invention, in the sixtieth aspect, the first source follower of the current amplification means includes two MOSFETs, and the second bias circuit of the current amplification means includes two MOSFETs corresponding to the two MOSFETs of the first source follower. Each MOSFET of the first source follower has polarity that is opposite to that of the corresponding MOSFET of the second bias circuit.
In accordance with a sixty-fourth aspect of the present invention, in the sixtieth aspect, the second bias circuit of the current amplification means includes: a third P-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means in the selective transmission step and whose drain is grounded; a third N-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means in the selective transmission step and whose drain is supplied with power supply voltage; a sixteenth resistor whose one end is supplied with the power supply voltage and whose other end is connected to the source of the third P-MOSFET; and a seventeenth resistor whose one end is connected to the source of the third N-MOSFET and whose other end is grounded.
In accordance with a sixty-fifth aspect of the present invention, in the sixty-fourth aspect, the first source follower of the current amplification means includes: a fourth N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the source of the third P-MOSFET; and a fourth P-MOSFET whose source is connected to the source of the fourth N-MOSFET and whose gate is connected to the source of the third N-MOSFET and whose drain is grounded. The output of the current amplification means is taken from wiring between the sources of the fourth N-MOSFET and the fourth P-MOSFET.
In accordance with a sixty-sixth aspect of the present invention, in the thirty-sixth aspect, the current amplification means which is used for the current amplification step includes: a fourth constant-current circuit; and a second source follower having single-ended push-pull (SEPP) structure.
In accordance with a sixty-seventh aspect of the present invention, in the sixty-sixth aspect, the fourth constant-current circuit is designed to have current mirror structure.
In accordance with a sixty-eighth aspect of the present invention, in the sixty-seventh aspect, the current amplification means includes: a fifth P-MOSFET whose gate is supplied with the driving signal that passed the selective transmission means in the selective transmission step; an eighteenth resistor whose one end is supplied with power supply voltage and whose other end is connected to the source of the fifth P-MOSFET; a fifth N-MOSFET whose drain is supplied with the power supply voltage and whose gate is connected to the source of the fifth P-MOSFET; a sixth N-MOSFET whose drain is connected to the drain of the fifth P-MOSFET; a seventh N-MOSFET whose drain is connected to the source of the fifth N-MOSFET and whose gate is connected to the gate of the sixth N-MOSFET and the drain of the fifth P-MOSFET; a nineteenth resistor whose one end is connected to the source of the sixth N-MOSFET and whose other end is grounded; and a twentieth resistor whose one end is connected to the source of the seventh N-MOSFET and whose other end is grounded. The output of the current amplification means is taken from wiring between the source of the fifth N-MOSFET and the drain of the seventh N-MOSFET.
In accordance with a sixty-ninth aspect of the present invention, in the thirty-seventh aspect, in the waveform generation step, variables which have preliminarily been stored for specifying the M types of waveforms are referred to and thereby the M waveforms are generated according to the variables.
In accordance with a seventieth aspect of the present invention, in the thirty-seventh aspect, the selective transmission means which is used for the selective transmission step includes M transfer gates each of which is composed of two MOSFETs.